This project covers the design and simulation of fundamental digital circuits using VHDL. It demonstrates the creation of essential components like an 8-bit register, a multiplexer, and a 4-bit full adder from the ground up. The project focuses on applying both dataflow and structural design methodologies to translate Boolean logic into functional, verifiable hardware descriptions.
Language: VHDL
Software: ModelSim
Core Concepts: Dataflow & Structural Modeling, Combinational Logic, Sequential Logic, Digital Simulation & Verification, Modular Design
VHDL Design Methodologies:
Dataflow Modeling: Described circuit behavior using concurrent signal assignments and Boolean expressions, such as Sum <= X xor Y xor Cin.
Structural Modeling: Built complex circuits by instantiating and connecting smaller, predefined components using concurrent port mapping.
Component Design & Implementation:
4-Bit Full Adder: Designed a 4-bit adder by cascading four 1-bit full adder components, where the carry-out of one stage becomes the carry-in for the next.
8-Bit Register: Created a register that stores an 8-bit input value on the rising edge of the clock when its 'Load' signal is active.
4-bit 8-to-1 Multiplexer: Implemented a MUX that uses a 3-bit select line to choose and pass one of eight 4-bit inputs to the output.
16-bit Tri-State Buffer: Modified a 14-bit buffer into a 16-bit version by padding the two most significant bits with '00'.
Simulation & Verification:
Performed rigorous testing in ModelSim to verify all circuit functionalities.
Validated the adder by applying test vectors where A=1111, B=1111, and Cin=0, which correctly resulted in a sum of 1110 and a carry-out of 1.
T-Flip Flop Freq. Divider
Counter Module
During this project, initial challenges included resolving file-saving issues within ModelSim, which was fixed by creating a new project structure. Additionally, initial errors in the multiplexer's select line mapping required iterative testing and debugging to correct.
Furthermore, this project provided critical hands-on experience with component instantiation and concurrent port mapping, which reinforced my understanding of modular circuit design. It improved my VHDL programming skills and prepared me for designing more complex digital systems.