Skills Overview

Language: VHDL

Software: Quartus

Hardware: DE1 Board, VGA

Core Concepts: VGA timing generation, PLL clocking, HSYNC/VSYNC pulse timing, active-region gating, pixel-to-memory address mapping, dual-port BRAM frame buffer, frame-synchronized cursor updates, FSM-based read/modify/write, reset sequencing and VRAM clearing

Technical Overview

Behavioral & Structural Modeling:
This system combines behavioral process logic (timing, cursor updates, FSM sequencing) with structural integration of a PLL, timing module, and memory subsystem into a single VGA graphics pipeline.

Component Design & Implementation

• pll (Pixel Clock Generator):
  Converts the board clock into a 108 MHz pixel clock required to drive 1280×1024 @ 60 Hz output.

• VGA Timing Generator (HSYNC/VSYNC + HPOS/VPOS):
  Implements horizontal and vertical counters that produce HPOS/VPOS and generate HSYNC/VSYNC pulses based on the active region and porch/sync intervals. RGB is driven only during the visible portion of the frame.

• Dual-Port VRAM (1-bit-per-pixel Frame Buffer):
  A dual-port block RAM stores drawing state persistently. One port is used by the draw FSM to read/modify/write memory, while the second port continuously reads the current pixel value for display. Pixel coordinates are mapped into a linear address, and the correct bit within the addressed byte is selected.

• Cursor Control (Frame-Synchronized):
  The cursor position is tracked by X/Y registers and updates once per frame to keep motion synchronized with the refresh cycle. Five switches provide directional motion, independent horizontal/vertical stopping, and reset. Boundary logic enables wrap-around at edges.

• Draw Control FSM (Read → Modify → Write):
  A three-state FSM writes one pixel per frame. It computes the cursor address, reads the byte containing the target bit, applies a mask to set the bit, and writes it back—creating the persistent white trail. During reset, this FSM also clears VRAM through controlled cycles.

Key Concepts on Display