Basic 4x1 MUX
Basic 4x1 MUX
This project covers the design and simulation of fundamental digital circuits using Verilog. It demonstrates the creation of key components such as a 2-to-1 multiplexer (dataflow and structural implementations) and a 4-to-1 multiplexer built hierarchically from smaller modules. The project emphasizes translating Boolean logic into synthesizable hardware through both dataflow and structural design methodologies, and it includes simulation and verification in ModelSim to ensure correct functionality.Â
Language: Verilog
Software: ModelSim
Core Concepts: Dataflow & Structural Modeling, Combinational Logic, Sequential Logic, Digital Simulation & Verification, Modular Design
Dataflow Modeling: Implemented 2-to-1 multiplexer behavior using continuous assign statements and Boolean expressions, e.g., y = (sel) ? b : a;.
Structural Modeling: Built the same 2-to-1 multiplexer by instantiating basic gates (AND, OR, NOT) and wiring them together to form the desired logic.
Component Design & Implementation:
2-to-1 Multiplexer (Dataflow): Designed a single-bit multiplexer using a single assignment statement for compact, readable code.
2-to-1 Multiplexer (Structural): Implemented the same multiplexer by explicitly connecting gate-level primitives for a hardware-accurate view.
4-to-1 Multiplexer: Created a 4-to-1 multiplexer using two cascaded 2-to-1 multiplexers and a final stage selector to pass one of four inputs to the output.
Simulation & Verification:
Simulated all designs in ModelSim, applying exhaustive select-line and input combinations to verify correct functionality.
Confirmed expected output behavior (e.g., selecting b when sel=1, verifying each input path in the 4-to-1 design).