The purpose of this project was to design and implement a 4-bit binary multiplier that takes two 4-bit inputs, calculates their product, and displays the result in a human-readable decimal format. The entire multi-step operation is controlled by a custom-designed state machine and a unique counter, ensuring that data is processed and displayed with correct timing on a DE1-SoC board.
Software: Quartus Prime, ModelSim
Hardware: DE1-SoC Board
Core Concepts: State Machine Design, Binary Multipliers, BCD Conversion, Digital Counters, Sequential Logic.
State Machine Control: A state machine was created to manage the control signals for the circuit. It coordinates the counting sequence and triggers the loading of the final product to the output at the correct moment.
Custom 1-2-3-4 Counter: The design features a specialized counter that follows a 1-2-3-4 sequence, resetting to zero after completing the cycle. This counter's state dictates the timing of the entire operation.
Timed Register Loading: An 8-bit register captures and holds the intermediate product values during the calculation. The final, stable product is only transferred from this register to the output when the counter reaches the fourth state.
BCD Conversion for Display: The final 8-bit binary product is converted into a Binary Coded Decimal (BCD) format. This allows the result to be displayed as a two-digit decimal number on the seven-segment display.
State Machine Step
1-4 Counter
Register Closer Look
Outer Look 8 bit Register
Multipler: State Machine, Register, and Cyclical Adder
Full Overview
The primary challenges in this project revolved around the timing synchronization between the state machine, counter, and the BCD conversion logic. These issues were successfully resolved through iterative testing and adjustments. The project resulted in a reliable circuit where a custom counter precisely controls data flow, ensuring that the system accurately calculates and displays the final product in a BCD format