Skills Overview

Language: Verilog

Software: Vivado (Synthesis, Implementation, Simulation)

Hardware: Nexys 4 Artix-7 Power Board

Core Concepts: Ripple-Carry Adder/Subtractor, Two’s Complement Arithmetic, Overflow Detection, Seven-Segment Display Decoding, Clock Division, Modular & Hierarchical Design, Digital Simulation & Timing Verification 

Technical Overview

Structural & Behavioral Modeling: Combined gate-level (Half_Adder, Full_Adder) and higher-level dataflow (assign statements) to build a modular arithmetic circuit.

Component Design & Implementation:

• fourbit_add_sub: Performs signed addition or subtraction using ripple-carry logic and two’s complement conversion.

• Full_Adder / Half_Adder: Primitive modules used to cascade carry signals and form the 4-bit adder.

• sev_seg_decoder: Converts binary outputs (0–F) to seven-segment patterns.

• sev_seg_with_clk: Implements a clock divider and time-multiplexing logic to drive multiple digits without flicker.

• addsub_display_wrapper: Top-level integration module connecting arithmetic, overflow detection, and display drivers.

Simulation & Verification:
Simulated in Vivado to confirm functional correctness and timing closure. Waveforms were used to verify overflow detection, sign handling, and proper multiplexing of digits.