Skills Overview

Language: VHDL

Software: ModelSim, Quartus

Hardware: DE1 Board

Core Concepts: Barrel Shifters, Arithmetic & Logical Shifts, Processor Architecture, Modular Design, Tristate Buffers, Bus Management

Technical Overview

• High-Speed Shifting: The core function is to shift a 16-bit input value by a signed 8-bit offset within a single clock cycle.

• Arithmetic & Logical Shifts: The design supports both arithmetic shifts, which preserve the sign bit, and logical shifts, which fill with zeros, determined by a control input.

• Modular VHDL Design: The system was built by integrating multiple functional VHDL components, including input registers, multiplexers, a core shift array, an OR/PASS logic unit, and tristate buffers for bus management.

• Flexible Control Logic: Shift operations are directed by an 8-bit signed control code and a HI/LO reference bit, which determines the positioning of the 16-bit data within the 32-bit output space.

• Shared Bus Integration: Tristate buffers are implemented to allow the final output registers to write results back onto shared data buses, a common and essential feature in processor design.

Key Concepts on Display

Wave Forms 

Time stamp explanations

• 0-200: loading the registers with the input and code for the shifting

• 200-300: First test (Lshift, hi, -5)

• 300-400: Third test (Ashift, hi, -5)

• 400-500: Fourth test (Ashift, lo, -5)

• 500-600: Second test (Lshift, hi, +5)

• 600-800: Enabling the tristate buffer to put the results from the FIRST mux (tribuffer 1) on the DMD and R

• 800-1000: Turn off the tristate buffer, change orpass into OR mode (0) and the results from the last shift was ORd with itself basically demonstrating orpass function

**a lot of the red were internal signals not used but was needed for the board demo**

Board Demos

Additional Comments 

A primary hurdle was orchestrating the precise signal timing required for data to propagate correctly across the multiple interconnected components. This demanded a meticulous approach to controlling the tristate buffers to prevent data bus contention. Furthermore, significant effort was dedicated to tailoring and reconfiguring logic to meet the specific I/O constraints necessary for the hardware demonstration.

This project was instrumental in honing my ability to integrate several smaller VHDL modules into a single, complex, and functional system. A key takeaway was developing a systematic method for troubleshooting, especially for diagnosing and reconciling mismatches between simulation waveforms and actual hardware behavior. Overall, the experience solidified my comprehension of advanced digital design, including sophisticated shift operations, register control, and effective bus management.