Skills Overview

Hardware: DE1-SoC FPGA Board

Software: Quartus Prime, ModelSim

Core Concepts: Asynchronous Design, Sequential Logic, Frequency Division, Digital Counters.

Technical Overview

• Precise Frequency Division: Designed a circuit to successfully reduce the board's 50MHz clock signal down to a stable 1Hz signal for accurate timekeeping. This was achieved by cascading a series of 21 T flip-flops.

• Asynchronous Counter Design: Implemented the clock using an asynchronous "cascade" design, where the counters for seconds, minutes, and hours are driven by the clock of the preceding digit.

• Custom 24-Hour Logic: Engineered specific logic to manage the 24-hour format. The circuit detects when the hours reach "23" and ensures the next state correctly rolls over to "00" instead of counting higher.

• Modular Design: The system was built from independent components for each time segment (hours, minutes, seconds), which were then integrated into a complete, functional system.

• Hardware Implementation: The entire design was programmed and tested on a DE1-SoC board using Quartus Prime.

Key Concepts on Display

Board Demos

Wave Forms

Additional Comments on Challenges Faced

A significant challenge was ensuring the timing signal was a precise 1Hz, as any instability would cause the clock to lose accuracy over time. Another hurdle was perfecting the logic for the hour digits to prevent the clock from displaying an invalid time (e.g., '24:00:00'). This required careful adjustments to ensure the reset function triggered correctly only after 23:59:59. 

Furthermore, this project provided a deep, practical understanding of frequency division and managing timing in digital design. It highlighted the complexities of handling propagation delays in asynchronous circuits and reinforced the importance of meticulous testing to ensure system reliability and accuracy.